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List of subject articles Radio frequency and Microwave Engineering


    • Open Access Article

      1 - A Novel Ultra-Broad Band, High Gain, and Low Noise Distributed Amplifier Using Modified Regulated Cascode Configuration (MRGC) Gain-Cell
      zainab baharvand Ahmad Hakimi
      In this paper, an ultra-broad bandwidth, low noise, and high gain-flatness CMOS distributed amplifier (CMOS-DA) based on a novel gain-cell is presented. The new gain-cell that enhances the output impedance as a result the gain substantially over conventional RGC is the Full Text
      In this paper, an ultra-broad bandwidth, low noise, and high gain-flatness CMOS distributed amplifier (CMOS-DA) based on a novel gain-cell is presented. The new gain-cell that enhances the output impedance as a result the gain substantially over conventional RGC is the improved version of Regulated Cascode Configuration (RGC). The new gain-cell based CMOS-DA is analyzed and simulated in the standard 0.13 μm-CMOS technology. The simulated results of the proposed CMOS-DA are included 14.2 dB average power gain with less than ± 0.5 dB fluctuations over the 3-dB bandwidth of 23 GHz while the simulated input and output return losses (S11 and S22) are less than -10 dB. The IIP3 and input referred 1-dB compression point are simulated at 15 GHz and achieved +8 dBm and -6.34 dBm, respectively. The average noise figure (NF) in the entire interest band has a low value of 3.65 dB, and the DC power dissipation is only 45.63 mW. The CMOS-DA is powered by 0.9 V supply voltage. Additionally, the effect of parameters variation on performance specifications of the proposed design is simulated by Monte Carlo simulations to ensure that the desired accuracy is yielded. Manuscript Document
    • Open Access Article

      2 - Design and Implementation of an Ultra-Wide Band, High Precision, and Low Noise Frequency Synthesizer
      Yas Hosseini Tehrani Nasser Masoumi
      This paper presents system-level design and implementation of an ultra-wide tunable, high precision, fast locking, low phase noise, and low power portable fractional-N frequency synthesizer. The output frequency of the proposed design is ranged from 54 MHz to 6.8GHz. Th Full Text
      This paper presents system-level design and implementation of an ultra-wide tunable, high precision, fast locking, low phase noise, and low power portable fractional-N frequency synthesizer. The output frequency of the proposed design is ranged from 54 MHz to 6.8GHz. The VCO cores cover frequencies from 3.4GHz to 6.8GHz. The programmable output dividers allow generation of the lower frequencies. The frequency resolution of the implemented system is ±20 parts per million (ppm) over -40/85ºC. The output power is tunable between -4dBm and +5dBm. The implemented system has a phase adjust feature that allows shifting of the output phase in relation to the reference oscillator ranged from 0° to 180°. It can generate a wide range, high precision, and linear frequency sweep. The sweep rate, frequency step, and frequency range are tunable. The new frequency tuning algorithm, named Yas algorithm, is proposed to improve frequency precision of the synthesizer. To demonstrate the efficiency of the Yas algorithm, the simulation result MATLAB and the experimental measurements are presented. The system consumes 300mA; therefore, it can be powered by Li-Ion battery. The output phase noise is -95.55 dBc/Hz at 1KHz offset from 3GHz. The experimental measurement results demonstrate that the implemented frequency synthesizer can be used for applications, such as oscillator of spectrum analyzer, automatic test equipment, FMCW radars, high-performance clock source for high speed data converter Manuscript Document