ARASP: An ASIP Processor for Automated Reversible Logic Synthesis
Subject Areas : IT Strategy
Zeinab Kalantari
1
*
,
Marzieh Gerami
2
,
Mohammad eshghi
3
1 - Department of Computer Engineering, Rafsanjan Branch, Islamic Azad University, Rafsanjan, Iran
2 - Department of Computer Engineering, Shahrekord Branch, Islamic Azad University, Shahrekord, Iran
3 - Faculty of Electrical and Computer Engineering, Shahid Beheshti University, Tehran, Iran
Keywords: Reversible logic, Optimization Algorithms, Application Specific Instruction Set Processors, ASIP, RTL.,
Abstract :
Reversible logic has been emerged as a promising computing paradigm to design low power circuits in recent years. The synthesis of reversible circuits is very different from that of non-reversible circuits. Many researchers are studying methods for synthesizing reversible combinational logic. Some automated reversible logic synthesis methods use optimization algorithms Optimization algorithms are used in some automated reversible logic synthesis techniques. In these methods, the process of finding a circuit for a given function is a very time-consuming task, so it’s better to design a processor which speeds up the process of synthesis. Application specific instruction set processors (ASIP) can benefit the advantages of both custom ASIC chips and general DSP chips. In this paper, a new architecture for automatic reversible logic synthesis based on an Application Specific Instruction set Processors is presented. The essential purpose of the design was to provide the programmability with the specific necessary instructions for automated synthesis reversible. Our proposed processor that we referred to as ARASP is a 16-bit processor with a total of 47 instructions, which some specific instruction has been set for automated synthesis reversible circuits. ARASP is specialized for automated synthesis of reversible circuits using Genetic optimization algorithms. All major components of the design are comprehensively discussed within the processor core. The set of instructions is provided in the Register Transform Language completely. Afterward, the VHDL code is used to test the proposed architecture.
[1] K. Kucukcakar, "An ASIP design methodology for embedded systems," in Proceedings of the Seventh International Workshop on Hardware/Software Codesign (CODES'99)(IEEE Cat. No. 99TH8450), 1999: IEEE, pp. 17-21.
[2] M. Gries and K. Keutzer, Building ASIPs: The Mescal Methodology. Springer Science & Business Media, 2006.
[3] R. F. Mirzaee and M. Eshghi, "Design of an ASIP IDEA crypto processor," in 2011 IEEE 2nd International Conference on Networked Embedded Systems for Enterprise Applications, 2011: IEEE, pp. 1-7.
[4] K. Shahbazi, M. Eshghi, and R. F. Mirzaee, "Design and implementation of an ASIP-based cryptography processor for AES, IDEA, and MD5," Engineering science and technology, an international journal, vol. 20, no. 4, pp. 1308-1317, 2017.
[5] M. Venkanna, R. Rao, and P. C. Sekhar, "An Efficient Design of ASIP Using Pipelining Architecture," in International Conference on Intelligent Computing and Applications, 2019: Springer, pp. 117-128.
[6] D. Große, X. Chen, G. W. Dueck, and R. Drechsler, "Exact SAT-based Toffoli network synthesis," in Proceedings of the 17th ACM Great Lakes symposium on VLSI, 2007, pp. 96-101.
[7] D. Bu and P. Wang, "An improved KFDD based reversible circuit synthesis method," Integration, vol. 69, pp. 251-265, 2019.
[8] T. Ahmed, A. Younes, and A. Elsayed, "Improving the quantum cost of reversible Boolean functions using reorder algorithm," Quantum Information Processing, vol. 17, no. 5, pp. 1-16, 2018.
[9] A. Basak, A. Sadhu, K. Das, and K. K. Sharma, "Cost Optimization Technique for Quantum Circuits," International Journal of Theoretical Physics, vol. 58, no. 9, pp. 3158-3179, 2019.
[10] Z. Kalantari, M. Eshghi, M. Mohammadi, and S. Jassbi, "Low-cost and compact design method for reversible sequential circuits," The Journal of Supercomputing, vol. 75, no. 11, pp. 7497-7519, 2019.
[11] M. Lukac, M. Perkowski, and M. Pivtoraiko, “Evolutionary approach to quantum and reversible circuits synthesis,” Artificial Intelligence Review Journal, vol. 20, no. 3–4, pp. 361–417, 2003.
[12] M. Lukac, M. Pivtoraiko, A. Mishchenko, and M. Perkowski, "Automated synthesis of generalized reversible cascades using genetic algorithms," 2002.
[13] M. Haghparast, M. Mohammadi, K. Navi, and M. Eshghi, "Optimized reversible multiplier circuit," Journal of Circuits, Systems, and Computers, vol. 18, no. 02, pp. 311-323, 2009.
[14] M. Mohammadi and M. Eshghi, "Heuristic methods to use don’t care in automated design of reversible and quantum logic circuits," Quantum Information Processing, vol. 7, no. 4, pp.175-192, 2008.
[15] M. Y. Abubakar and L. T. Jung, "Synthesis of Reversible Logic Using Enhanced Genetic Programming Approach," in 2018 4th International Conference on Computer and Information Sciences (ICCOINS), 2018: IEEE, pp. 1-5.
[16] T. Atkinson, A. Karsa, J. Drake, and J. Swan, "Quantum program synthesis: Swarm algorithms and benchmarks," in European Conference on Genetic Programming, 2019: Springer, pp. 19-34.
[17] R. Landauer, "Irreversibility and heat generation in the computing process," IBM journal of research and development, vol. 5, no. 3, pp. 183-191, 1961.
[18] C. H. Bennett, "Logical reversibility of computation," IBM Journal of Research and Development, vol. 17, no. 6, pp. 525-532, 1973.
[19] R. P. Feynman, "Quantum mechanical computers," Foundations of Physics, pp. 507-531, 1986.
[20] M. P. Frank, "Introduction to reversible computing: motivation, progress, and challenges," in Proceedings of the 2nd Conference on Computing Frontiers, 2005, pp. 385-390.
[21] E. Fredkin and T. Toffoli, "Conservative logic," International Journal of theoretical physics, vol. 21, no. 3, pp. 219-253, 1982.